A thorough design review before sending your PCB to fabrication saves time, money, and frustration. Catching a missing via, wrong footprint, or clearance violation at the review stage costs nothing. Catching it after fabrication costs a full respin — typically ₹2,000-10,000 and 1-3 weeks of delay. This comprehensive checklist covers every aspect of PCB review, from schematic verification to manufacturing file checks, organised in the order you should perform them.
Table of Contents
- Schematic Review
- Footprint Verification
- Layout and Routing Review
- Power Distribution Check
- Manufacturing File Review
- BOM Verification
- Final Sign-Off Checks
- Frequently Asked Questions
Schematic Review
- ☐ Run ERC (Electrical Rules Check) — resolve all errors, review all warnings
- ☐ Every IC power pin is connected (not left floating)
- ☐ Decoupling capacitors on every IC power pin (100nF minimum)
- ☐ Pull-up/pull-down resistors on all required pins (I2C SDA/SCL, SPI CS, reset, enable)
- ☐ Crystal oscillator load capacitors match the crystal datasheet
- ☐ Reset circuit with proper RC time constant and optional manual reset button
- ☐ ESD protection on all external-facing signals (USB, HDMI, GPIO headers)
- ☐ Voltage levels match between all connected ICs (3.3V ↔ 5V level shifting where needed)
- ☐ Connector pinouts match the cable/mating connector (verify mirror orientation)
- ☐ Test points on critical signals: power rails, I2C bus, UART TX/RX, reset, key GPIOs
- ☐ Net names are meaningful (not generic Net001, Net002)
Footprint Verification
- ☐ Every component footprint matches the manufacturer’s recommended land pattern
- ☐ Pin 1 marking on all IC footprints matches the datasheet
- ☐ Polarity markings correct on all electrolytic capacitors, diodes, and LEDs
- ☐ Through-hole components: hole sizes accommodate the actual lead diameter (hole = lead diameter + 0.2mm minimum)
- ☐ Connector footprints verified against the actual connector (print a 1:1 scale PDF and physically test fit)
- ☐ Mounting holes: correct diameter (M3 = 3.2mm hole, M2.5 = 2.7mm), plated or non-plated as intended
- ☐ 3D model check: no component collisions, height clearance within enclosure limits
- ☐ Thermal pads on QFN/DFN packages: correct size with solder paste openings and thermal vias
Layout and Routing Review
- ☐ Run DRC (Design Rules Check) — zero errors
- ☐ All nets routed (no ratsnest/airwires remaining)
- ☐ Minimum trace width meets fabricator capability (0.15mm for standard)
- ☐ Minimum clearance meets fabricator capability (0.15mm for standard)
- ☐ No traces crossing ground plane splits
- ☐ Differential pairs: matched length, constant spacing, no sharp bends
- ☐ Controlled impedance traces: correct width per stack-up calculation
- ☐ Power traces adequately wide for their current (use IPC-2221 calculator)
- ☐ No copper slivers or isolated copper islands
- ☐ Ground pour with dead copper removed
- ☐ Via stitching around board perimeter and near signal layer transitions
- ☐ Board edge clearance: 0.5mm minimum for all copper
- ☐ High-voltage clearances per IPC-2221 (230V AC needs 2.5mm on external layers)
Power Distribution Check
- ☐ All voltage rails connected from regulator to every consuming IC
- ☐ Bulk capacitors (10-100µF) at each regulator output
- ☐ Local decoupling capacitors placed within 2mm of each IC power pin
- ☐ Power trace voltage drop calculated and within 3% of supply voltage
- ☐ Total current draw does not exceed regulator capacity (include 20% margin)
- ☐ Reverse polarity protection on the power input (if battery or external supply)
- ☐ Power-on sequencing correct for multi-rail designs (e.g., 3.3V before 1.8V for some MCUs)
- ☐ Thermal pads on voltage regulators connected to adequate copper area and thermal vias
Manufacturing File Review
- ☐ Generate Gerber files and open in a standalone Gerber viewer (not the EDA tool)
- ☐ Verify all layers present: top copper, bottom copper, inner layers, top mask, bottom mask, top silk, bottom silk, drill file, board outline
- ☐ Board outline is a closed shape with no gaps
- ☐ Drill file contains all hole sizes and locations
- ☐ Silkscreen does not overlap pads or vias
- ☐ Solder mask openings correctly expose all pads
- ☐ Fiducial marks present (if assembly will be automated)
- ☐ Fabrication drawing/notes included: layer count, board thickness, copper weight, surface finish, solder mask colour, special requirements
BOM Verification
- ☐ Every component in the BOM has a valid manufacturer part number
- ☐ All components are in stock at your preferred supplier (check Mouser, DigiKey, LCSC, or local Indian distributors)
- ☐ No obsolete or NRND (Not Recommended for New Design) components
- ☐ Alternate/second-source parts listed for critical components
- ☐ Component values match the schematic (double-check after any last-minute changes)
- ☐ Package sizes are consistent with your assembly capability (no 0201 if hand soldering)
- ☐ BOM quantities include assembly loss allowance (order 5-10% extra for passives)
Final Sign-Off Checks
- ☐ Board dimensions match the enclosure
- ☐ Mounting holes align with the enclosure standoffs
- ☐ Connector positions match enclosure cutouts
- ☐ Panelization requirements discussed with the assembly house
- ☐ Version number and date on the silkscreen
- ☐ If applicable: regulatory marking placeholders (CE, BIS, RoHS) on silkscreen
- ☐ File naming convention follows the fabricator’s requirements
- ☐ Upload to the fabricator’s website and review their automated DFM check results
Frequently Asked Questions
How long should a design review take?
For a simple 2-layer board: 1-2 hours. For a 4+ layer board with high-speed signals: 4-8 hours. Never rush the review — it is the cheapest quality assurance step in your entire product development cycle. Some teams do peer reviews where a second engineer checks the design with fresh eyes.
Should I use the manufacturer’s DFM check or do my own?
Both. Do your own review first using this checklist, then upload to the fabricator and review their automated DFM results. Automated checks catch mechanical violations (clearance, drill size, board edge) but miss functional issues (wrong footprint, missing decoupling, impedance errors).
What is the most common PCB design mistake?
Wrong footprint — specifically, the physical pad layout does not match the actual component. This is especially common with SOT-23 variants (different manufacturers use different pinouts), QFN packages (wrong thermal pad size), and connectors (wrong pitch or pin count). Always verify footprints against the manufacturer’s datasheet, not generic library parts.
How do I do a 1:1 print check?
Export your PCB layout as a PDF at 1:1 scale (no fit-to-page scaling). Print on A4 paper and physically place your components on the printout. Check that connector holes align, IC pads match the package, and mounting holes line up with your enclosure. This 5-minute check has saved countless designers from expensive respins.
What should I do if I find a problem after ordering?
Contact the fabricator immediately. If they have not started production, they may allow you to update files. If production has started, assess whether the problem is cosmetic (proceed), functional but fixable with rework (proceed and modify after receiving), or fatal (cancel and reorder). Most fabricators have a brief window where changes are possible.
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