PCB Routing: Trace Width, Via, and Clearance Rules

PCB routing is the process of connecting component pads with copper traces according to the schematic netlist. While modern auto-routers can handle simple designs, complex boards still require manual routing guided by electrical and manufacturing constraints. This guide covers the fundamental routing rules — trace width selection, via usage, clearance requirements, and routing strategies — that every Indian PCB designer needs to master for reliable, manufacturable boards.

Table of Contents

• Trace Width Selection
• Clearance Rules
• Via Usage Guidelines
• Routing Order Strategy
• Trace Corners and Bends
• Differential Pair Routing
• DFM Routing Rules
• Frequently Asked Questions

Trace Width Selection

Trace width depends on three factors: current capacity, impedance requirements, and manufacturing capability.

The absolute minimum trace width at most Indian fabricators is 0.1mm (4 mil), but 0.15mm (6 mil) is the practical minimum for reliable yield. For budget orders at JLCPCB or PCBWay, stick to 0.15mm minimum.

Clearance Rules

For high-voltage circuits (above 50V), increase clearances per IPC-2221: approximately 0.1mm per volt for internal layers and 0.5mm per 100V for external layers (varies with coating and altitude). Mains voltage (230V AC in India) requires 2.5mm minimum clearance on external uncoated surfaces.

Via Usage Guidelines

• Standard via: 0.3mm drill, 0.6mm pad — use as default
• Small via: 0.2mm drill, 0.45mm pad — use for dense routing between IC pins
• Power via: 0.4-0.5mm drill — use for power connections, multiple vias in parallel
• Thermal via: 0.3mm drill in array — use under exposed thermal pads

Minimise the number of vias per net. Each via adds approximately 0.5pF capacitance and 1nH inductance. For high-speed signals, route on a single layer if possible. When layer changes are necessary, place ground vias near signal vias to provide a return current path.

Routing Order Strategy

1. Power rails first: Route the widest, most constrained nets first. Use copper pour where possible
2. Critical signals next: Clocks, high-speed differential pairs, analog signals — route manually with care
3. Bus signals: Address/data buses should be routed together with matched lengths if required
4. General signals: GPIO, control lines, LED connections — auto-router can handle these
5. Ground last: Fill remaining copper area with ground pour

Always route on a grid. Use 0.25mm (10 mil) grid for signal routing and 0.05mm (2 mil) for fine adjustments near pads. Snap all trace segments to the grid to avoid manufacturing tolerance issues.

Trace Corners and Bends

• 90-degree corners: Avoid for any signal above 100 MHz. The acute inner angle concentrates current and can cause impedance discontinuities
• 45-degree corners: Standard practice. Two 45-degree bends replace one 90-degree corner
• Arc corners: Best for impedance continuity. KiCad 7+ and Altium support arc routing
• For low-speed signals: 90-degree corners are electrically fine below 100 MHz but look unprofessional. Use 45-degree as a habit

Differential Pair Routing

USB, HDMI, Ethernet, and LVDS require matched differential pair routing:

• Route both traces together with constant spacing
• Length-match to within 0.1mm for USB 2.0, 0.05mm for USB 3.0
• Avoid routing near board edges or over plane splits
• When both traces change layers, use matched via pairs with identical structures
• Keep other signals at least 3x the pair gap distance away
• Use your EDA tool’s differential pair routing mode — manual pair routing is error-prone

DFM Routing Rules

Design for Manufacturing (DFM) rules prevent fabrication issues:

• Acid traps: Acute angles (less than 45°) where traces meet can trap etchant and cause over-etching. Avoid angles below 45°
• Slivers: Very thin copper areas (under 0.1mm wide) between traces may not etch cleanly. Use DRC to check
• Starved thermals: Thermal relief spokes thinner than 0.2mm may not plate reliably. Set thermal spoke width to 0.25mm minimum
• Teardrop pads: Add teardrops where traces meet pads to prevent drill breakout from severing the trace-to-pad connection
• Copper balance: Distribute copper evenly across the board to prevent bowing during lamination. Add copper fill (ground pour) to empty areas

Frequently Asked Questions

Should I use auto-router or route manually?

Route critical signals (power, clocks, differential pairs, analog) manually, then use the auto-router for remaining simple connections. Auto-routers in KiCad (Freerouting) work well for GPIO and digital logic connections but produce poor results for power and high-speed signals.

How many layers do I need?

2 layers for simple designs (Arduino shields, breakout boards). 4 layers when you need impedance control, a dedicated ground plane, or have more than 100 connections. 6+ layers for complex MCU designs with DDR memory, multiple power rails, and high-speed interfaces.

What is the minimum trace-to-edge clearance?

0.3mm absolute minimum, 0.5mm recommended. The board outline routing process removes material with a 2mm router bit, and registration tolerance is ±0.1mm. Copper closer than 0.3mm to the edge may be exposed or damaged.

Can I route traces under ICs?

Yes, but only on different layers. Do not route unrelated signals on the same layer directly under an IC — it makes rework impossible. On inner layers, routing under ICs is standard practice and often necessary for breakout.

How do I handle unrouted nets (rats nest)?

Run DRC regularly during routing to check for unconnected nets. If a net cannot be routed without violating clearance rules, consider adding a via to route on another layer, widening the board slightly, or moving components to create more routing space.

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