Cascode Amplifier: High Frequency and Low Noise Design

Cascode Amplifier: High Frequency and Low Noise Design

When your standard common-emitter amplifier starts losing gain as frequency rises, or when noise figures become unacceptably high in RF front-end circuits, it’s time to study cascode amplifier design. The cascode topology stacks two transistors in series to defeat the Miller effect, extend bandwidth dramatically, and deliver lower noise than single-stage designs. Used everywhere from LNA (low noise amplifier) circuits to oscilloscope front ends to radio receivers, the cascode is a must-know topology for any serious electronics engineer or advanced hobbyist.

What Is a Cascode Amplifier?

A cascode amplifier consists of two transistor stages connected in series: the first operates as a common-emitter (CE) or common-source (CS) stage, while the second operates as a common-base (CB) or common-gate (CG) stage. The input signal enters the bottom transistor (CE/CS) and the output is taken from the collector/drain of the top transistor (CB/CG).

This arrangement has three major advantages over a simple CE or CS amplifier:

• Drastically reduced Miller capacitance: The common-base stage presents a very low input impedance (approximately 1/gm) to the collector of the CE stage, making the voltage gain of that stage close to unity. This almost eliminates Miller multiplication of the collector-base capacitance (Cbc).
• Higher bandwidth: With Miller capacitance minimised, the -3 dB frequency can extend into the hundreds of MHz with common BJTs.
• Better reverse isolation: The CB stage shields the input from output load changes, improving stability and reducing feedback from output to input.

The cascode is widely used in RF preamplifiers, VHF/UHF tuner front ends, oscilloscope input stages, instrumentation amplifiers, and low-noise amplifiers for radio astronomy and SDR (software-defined radio) setups — all areas where Indian hobbyists are increasingly active.

BC547 NPN Transistor (Pack of 10)

The BC547 is an excellent transistor for building audio-frequency and lower RF cascode amplifiers. High hFE and low noise make it a go-to for hobbyist cascode experiments.

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The Miller Effect: Why Bandwidth Suffers

To understand why the cascode is so powerful, you first need to understand the Miller effect — the single biggest enemy of bandwidth in transistor amplifiers.

In a common-emitter BJT amplifier with voltage gain Av, the collector-base capacitance (Cbc, typically 2–10 pF) is effectively multiplied by the factor (1 + |Av|) when referred to the input side. This is the Miller capacitance:

C_Miller = C_bc × (1 + |A_v|)

If Av = -100 and Cbc = 4 pF, then C_Miller = 404 pF. This large capacitance at the input, combined with the source resistance, forms an RC low-pass filter that severely limits bandwidth. For example, with a source resistance of 1 kΩ, the bandwidth would be:

f_-3dB = 1 / (2π × 1000 × 404×10^-12) ≈ 394 kHz

That’s less than 400 kHz for a circuit with perfectly good transistors. Now, in a cascode, the CE stage sees a load resistance of approximately 1/gm of the CB stage (where gm ≈ Ic/26 mV at room temperature). For Ic = 1 mA, gm = 38.5 mS, so 1/gm ≈ 26 Ω. The gain of the CE stage becomes approximately -gm1 × (1/gm2) ≈ -1. This makes C_Miller ≈ 2 × Cbc — essentially just the bare capacitance, a 200× improvement!

BJT Cascode Configuration: Theory and Analysis

A typical NPN-NPN BJT cascode circuit has the following structure:

• Q1 (bottom, CE stage): Signal input at base, emitter grounded via bypass capacitor, collector drives Q2 emitter directly
• Q2 (top, CB stage): Base held at fixed AC-ground bias voltage, emitter is input (from Q1 collector), collector is output
• Resistive load R_L: Connected from Q2 collector to V_CC

Voltage Gain: The total voltage gain is approximately:

A_v ≈ -g_m1 × R_L

This is the same as a CE amplifier — the cascode doesn’t sacrifice voltage gain. What it gains is bandwidth and isolation.

Input Impedance: The cascode input impedance is the same as a CE stage — high, and dominated by the bias resistors. This makes it easy to drive from high-impedance sources.

Output Impedance: The CB stage provides very high output impedance (comparable to a current source), which helps maintain gain when driving varying load impedances. This is particularly useful in tuned RF amplifiers where the load is a parallel LC tank circuit.

Example BJT Cascode Design (for 10 MHz operation):

• Transistors: two BC547B (ft ≈ 300 MHz)
• Supply: 12 V (from SMPS)
• Quiescent current: Ic = 2 mA (good noise/gain compromise)
• Load: 2.2 kΩ (for Av ≈ -170)
• Q1 bias: Voltage divider R1=68k, R2=10k for Vb1 ≈ 1.5 V, Ve1 = 0.8 V
• Q2 bias: Voltage divider for Vb2 ≈ 7 V (places Q2 collector well above Q2 emitter)
• Bypass caps: 100 nF on Q1 emitter, 100 nF on Q2 base (to AC-ground the base)
• Coupling caps: 100 nF at input and output

0.1µF 50V Capacitor (Pack of 50)

Essential bypass and coupling capacitors for cascode amplifier circuits. These 100 nF capacitors are ideal for decoupling the cascode base bias and coupling signals between stages.

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JFET and MOSFET Cascode Designs

FET cascode amplifiers follow the same principle but use JFETs or MOSFETs instead of BJTs. The bottom transistor operates as a common-source (CS) stage and the top operates as common-gate (CG).

FET cascodes are particularly popular for:

• Very high input impedance: JFET gate impedance is essentially infinite, making them ideal for high-impedance sensor interfaces and electrometer amplifiers
• Low flicker (1/f) noise: JFETs typically exhibit less low-frequency noise than BJTs
• VHF/UHF LNA: GaAs or SiGe FETs in cascode achieve noise figures below 0.5 dB

For a simple JFET cascode using two J2N3819 (or equivalent) N-channel JFETs:

• Q1 source to GND via 330 Ω (sets Vgs and Idss operating point)
• Q1 gate: signal input via 1 MΩ gate resistor to maintain input impedance
• Q1 drain connects directly to Q2 source
• Q2 gate: bypassed to GND via 100 nF (AC-ground)
• Q2 drain: load resistor to V+ and output coupling capacitor

For MOSFET cascodes in power applications (like high-side switches), two enhancement-mode N-channel MOSFETs can be stacked. The top MOSFET gate is biased at a fixed intermediate voltage. This technique is used to allow low-voltage rated MOSFETs to handle high voltages collectively — common in GaN power electronics.

Biasing the Cascode: Practical DC Design

Proper biasing is the most critical and often most confusing aspect of cascode design. Here’s a systematic approach for an NPN BJT cascode:

Step 1: Choose Quiescent Current (Ic)

For general-purpose RF work, 1–5 mA is a good starting point. Higher Ic improves gm (and thus gain and bandwidth) but increases power consumption and noise contribution from the load resistor.

Step 2: Set Q1 (CE Stage) Operating Point

Allow Vce1 ≈ 1–2 V for Q1. The collector of Q1 = emitter of Q2. Target Vce1 = 1.5 V:

• Ve1 = Ic × Re = 0 (if no emitter resistor) or small
• Vb1 = Vbe + Ve1 ≈ 0.7 V (simple case)

Step 3: Set Q2 (CB Stage) Base Voltage

Q2’s base needs to be at a fixed DC level such that both Q2 and Q1 have adequate Vce for linear operation:

• Vb2 = Vce1 + Vbe2 = 1.5 + 0.7 = 2.2 V (minimum)
• Practical: set Vb2 to V_CC/3, e.g., 4 V for 12 V supply

Step 4: Set Load Resistor

RL = (V_CC − Vb2 − Vce2_min) / Ic

For Vcc=12 V, Vb2=4 V, Vce2_min=2 V, Ic=2 mA: RL = (12−4−2)/0.002 = 3 kΩ

Step 5: Design Bias Voltage Dividers

Use voltage dividers with current ≥10 × Ib to ensure stability. For Ic=2 mA, hFE=200, Ib=10 µA, design divider current ≥100 µA.

1/4W Metal Film Resistors (Pack of 100)

Metal film resistors offer lower noise than carbon film — important for low-noise cascode amplifier bias networks. Ideal for precision amplifier designs.

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Low Noise Amplifier Application

The cascode topology naturally lends itself to LNA (low noise amplifier) design because the common-base/common-gate second stage contributes very little noise to the overall circuit. The noise figure is essentially determined by the first transistor (Q1) and its source matching.

For an SDR (RTL-SDR or HackRF) LNA operating at 100–300 MHz using a cascode with BC547B transistors:

• Input matching: 50 Ω coaxial input matched using an LC network
• Q1 emitter degeneration: small (22 Ω) to improve noise match at the cost of slight gain reduction
• Q2 collector load: tuned parallel LC (resonant at signal frequency) for maximum gain
• Expected noise figure: 3–6 dB (not professional LNA level, but useful for experimentation)
• Expected gain: 15–25 dB

For serious SDR work with noise figures below 1 dB, purpose-built LNA modules using MMIC (Monolithic Microwave Integrated Circuit) chips like the SPF5189Z or BGA2803 are recommended. But the BJT cascode is an excellent learning platform and performs surprisingly well at HF and lower VHF frequencies.

Building and Testing a Cascode Circuit

Building your first cascode amplifier on a breadboard is straightforward if you follow these steps:

Materials Needed

• 2× BC547 NPN transistors
• Resistors: 68k, 10k, 10k, 5.6k, 3.3k, 100Ω, 470Ω (assorted values)
• Capacitors: 3× 100 nF (ceramic), 2× 10 µF electrolytic
• 12 V power supply
• Breadboard and jumper wires
• Multimeter for DC bias verification

Testing Procedure

1. DC bias check first: Before applying any signal, measure DC voltages at all nodes. Q1 base should be ~1–2 V, Q1 collector ≈ Q2 emitter should be ~3–4 V, Q2 collector should be ~8–10 V (for 12 V supply).
2. Signal injection: Apply a small sine wave (10–50 mV peak) at the amplifier input from a function generator or audio oscillator.
3. Measure gain: Compare output amplitude to input amplitude with an oscilloscope. Expected gain: 50–200× depending on RL and Ic.
4. Frequency sweep: Increase frequency and note when gain drops by 3 dB. Compare with a standalone CE amplifier built from one BC547 — the cascode should extend -3 dB point by 10–50× in frequency.

10×10 cm Universal PCB Prototype Board

Once you’ve verified your cascode design on a breadboard, transfer it to this universal PCB for a more permanent and RF-stable build. Shorter traces mean less parasitic inductance.

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Frequently Asked Questions

Q1: How much bandwidth improvement does a cascode give over a common-emitter stage?

Typically 10× to 100× improvement in -3 dB bandwidth, depending on the transistors used and circuit impedances. A CE amplifier with BC547 might be limited to a few hundred kHz due to Miller effect, while a cascode can extend this into the tens of MHz.

Q2: Does a cascode amplifier have more voltage gain than a CE amplifier?

The overall voltage gain is approximately the same (Av ≈ -gm × RL). The key advantage is that this gain is maintained at much higher frequencies. The cascode doesn’t sacrifice gain for bandwidth — it achieves both.

Q3: Can I build a cascode amplifier on a breadboard?

Yes, for audio and low RF frequencies up to a few MHz. At higher frequencies, breadboard parasitic capacitances and lead inductances begin to matter. For VHF and above, use a compact PCB with short traces and solid ground planes.

Q4: What is the difference between a cascode and a cascade amplifier?

A cascade (cascaded) amplifier connects stages in series with output of one driving input of the next — each stage has its own load and bias, and the stages are coupled via capacitors. A cascode stacks two transistors vertically sharing the same DC current path, with the second transistor’s base/gate held at a fixed AC-ground potential. They are very different topologies.

Q5: Is the cascode used in modern IC amplifiers?

Absolutely. Cascode structures are extensively used in op-amp designs (folded cascode op-amps achieve bandwidths in the GHz range), RF LNAs, current mirrors, and differential amplifiers inside virtually every analog IC. Understanding discrete cascode circuits gives you direct insight into how these ICs work internally.