PCB DRC Checks: Design Rule Errors and How to Fix Them

Design Rule Check (DRC) is an automated verification process that scans your PCB layout for violations of electrical, manufacturing, and safety rules. Running DRC before submitting Gerber files to a fabrication house catches errors that would otherwise result in boards that do not assemble, do not pass electrical testing, or do not meet the fab’s manufacturing capabilities.

This guide explains the most common DRC errors in KiCad and EasyEDA, what causes them, and exactly how to fix each one — saving you costly respins and rework.

What Is PCB DRC?

DRC checks your PCB layout against a set of rules that define minimum feature sizes, clearances, and connectivity requirements. DRC is distinct from ERC (Electrical Rules Check), which validates the schematic. DRC operates on the physical board layout.

Types of DRC violations:

• Electrical violations: Shorts (copper from different nets touching), unconnected nets (ratsnest not routed)
• Manufacturing violations: Trace/space/via too small for the fab’s capabilities, annular rings too small
• Physical violations: Component courtyards overlapping, components outside board boundary
• Silkscreen violations: Text or graphics overlapping pads

Setting Up DRC Rules in KiCad

In KiCad PCB Editor, DRC rules are configured in:

1. File > Board Setup > Design Rules (for global rules)
2. Inspect > Design Rules Checker (to run DRC)

Standard Design Rules for JLCPCB/PCBWay

Custom Net Classes

In KiCad, you can assign different DRC rules to different net classes. Common setup:

• Default: 0.2mm trace width, 0.2mm clearance
• Power: 0.5mm trace width, 0.3mm clearance (for VCC/GND traces carrying high current)
• HighSpeed: Controlled impedance width (e.g., 0.28mm for 50 ohm microstrip), 0.2mm clearance

Clearance and Spacing Errors

“Clearance Violation” — Copper Too Close

Cause: Two copper items from different nets are closer than the minimum clearance rule.

Fix:

• Identify the two offending pads/traces in the DRC results list — DRC highlights them
• Move the trace routing around the obstacle, increasing the gap
• If two pads are inherently close (e.g., 0.4mm pitch QFN), ensure your board rules match the component pitch — you may need to use tighter design rules (set clearance to 0.1mm for high-density net class)
• If it is a copper pour touching a pad of another net: increase the pour clearance value in the zone properties

“Short Circuit” — Two Different Nets Connected

Cause: Copper from net A is touching copper from net B. Catastrophic — will cause the board to fail electrical test.

Fix:

• Zoom into the DRC-highlighted location
• Check if a trace accidentally routes through a pad of a different net
• Check if a copper pour floods over a gap that is too narrow (increase pour clearance or add a keepout zone)
• Check if a component footprint has pads with incorrect net assignments — go back to schematic and check

“Track End Off Pad” or “Track not Connected”

Cause: A trace ends just short of the pad center or does not reach the pad annular ring.

Fix: Select the trace end and drag it to snap onto the pad center. In KiCad, trace ends should snap to pad centers automatically — if not, ensure snapping is enabled and pads are at grid points.

Unconnected Nets

“Unconnected” / “Ratsnest” Errors

Cause: A net exists in the schematic but has no copper route connecting it on the PCB. Shown as a thin “ratsnest” line between unconnected pads.

Fix options:

• Route the missing connection with a trace
• If intentionally not connecting (e.g., a no-connect flag in the schematic): add a No-Connect marker (X) in the schematic on that pin, re-update PCB from schematic, and re-run DRC — the ratsnest will disappear
• If a global net (like GND) appears as unconnected: ensure copper pour is using the correct net name and is flooding to the pads. Re-run fill zones (Edit > Fill All Zones in KiCad).

Missing Ground Connections

A common scenario: all GND pads connect to a copper pour, but the pour was not updated after moving components. Fix: Edit > Fill All Zones (shortcut: B in KiCad PCB editor). Re-run DRC after filling.

Courtyard Violations

“Courtyard Overlap” / “Component Courtyards Intersect”

Cause: Two components are placed too close — their courtyard boundaries overlap. Courtyards define the keepout zone for each component. Overlapping courtyards indicate the components cannot physically coexist without collision or soldering issues.

Fix:

• Move one component away until courtyards no longer overlap
• If you need extreme density: verify whether the actual component bodies and solder fillets truly conflict, or if the courtyard is overly conservative. You can modify the courtyard in the footprint editor — but do this carefully and only when you have verified the physical clearances manually.

“Component Outside Board Area”

Cause: A footprint’s courtyard or body extends beyond the board outline.

Fix: Move the component inside the board boundary, or extend the board outline to encompass the component.

Silkscreen Violations

“Silkscreen Over Pad”

Cause: A silkscreen element (text, graphic, or component outline) overlaps an exposed copper pad.

Fix:

• Select the silkscreen reference text of the offending component and move it away from the pads
• If the footprint outline on F.SilkS is the issue: edit the footprint, trim the silkscreen line segments that overlap pads
• Some fabs automatically trim silkscreen over pads — JLCPCB does this. But it is still better practice to eliminate the overlap.

“Silkscreen Outside Board”

Cause: Text or graphics on the silkscreen layer extend beyond the board outline.

Fix: Trim or move the silkscreen element inside the board boundary. Minimum 0.3mm clearance from board edge recommended.

Annular Ring and Via Errors

“Via Annular Ring Too Small”

Cause: The copper ring around a drilled hole (annular ring) is smaller than the minimum required. Thin annular rings are fragile and prone to pad lifting during assembly.

Fix:

• Increase the via size (outer pad diameter). For a 0.3mm drill, use at least 0.6mm pad diameter (0.15mm annular ring each side)
• JLCPCB minimum: 0.13mm annular ring. Recommended: 0.15mm minimum

“Drill Out of Range”

Cause: Via or through-hole drill size smaller than the fab’s minimum drill capability (typically 0.2mm for JLCPCB standard service).

Fix: Increase the drill diameter. For most designs, use 0.3mm via drill as the minimum practical size.

“Via in Solder Mask” / “Via Tent” Issues

KiCad creates tented vias (solder mask covering) by default. If you explicitly need untented vias (for testing or heat dissipation), check that your via tenting settings match your intent. Untented vias on tight-pitch SMD areas can cause solder bridging during assembly.

Footprint and Pad Errors

“Pad Drill Out of Range” or “Missing Drill”

Cause: A through-hole pad has no drill or the drill diameter is zero (common when importing footprints from other tools).

Fix: Select the pad, open pad properties (E key), verify drill size is set correctly.

“Pad With No Net”

Cause: A pad exists in the footprint but has no net assigned. This is sometimes intentional (mechanical pads, test pads, no-connect pins).

Fix: If intentional, add a No-Connect marker to the corresponding pin in the schematic. If unintentional, verify the schematic symbol and footprint have matching pin counts and the net is properly connected.

EasyEDA DRC

In EasyEDA Standard Edition:

1. In PCB editor, go to Design > Design Rule Check
2. Set clearance rules in the DRC settings panel
3. Run the check — violations are highlighted in the DRC results list
4. Click on a violation in the list to zoom to the location

EasyEDA’s DRC is less configurable than KiCad’s but checks the most critical issues: clearance violations, unconnected nets, and copper shorts. Always run DRC before ordering from JLCPCB — use the built-in Gerber viewer as a secondary check.

Pre-Fabrication DRC Workflow

Before submitting Gerbers to any fab house, follow this workflow:

1. Fill all copper zones: Edit > Fill All Zones (or press B) in KiCad. Copper pours may have unfilled areas from earlier edits.
2. Run DRC: Inspect > Design Rules Checker. Resolve ALL violations except:
   • “Footprint missing 3D model” (cosmetic only)
   • “No-connect” markers you have explicitly placed
3. Check unconnected nets list: Ensure zero unconnected nets (unless intentional no-connects)
4. Export Gerbers
5. Open Gerbers in viewer (KiCad Gerber Viewer or JLCPCB online viewer)
6. Re-run DRC on the Gerbers — some fabs offer Gerber DRC. PCBWay has a built-in Gerber DRC tool.
7. Order

Frequently Asked Questions