PCB for Ethernet: Magnetics and PHY Layout Guide

Ethernet is the backbone of networked electronics — from industrial controllers to IoT gateways. Designing an Ethernet PCB involves the PHY (Physical Layer) IC, magnetics (transformer module), and the RJ45 connector, all connected by carefully routed differential pairs. The key challenge is maintaining signal integrity at 100 Mbps (100BASE-TX) or 1 Gbps (1000BASE-T) while providing galvanic isolation through the magnetics module. This guide covers practical Ethernet PCB layout for Indian designers.

Table of Contents

• Ethernet Architecture
• PHY IC Layout
• Magnetics Selection and Placement
• Differential Pair Routing
• RJ45 Connector Layout
• Galvanic Isolation
• Common Design Patterns
• Frequently Asked Questions

Ethernet Architecture

A typical Ethernet interface on a PCB consists of:

1. MAC (Media Access Controller): Usually integrated in the MCU or SoC
2. PHY IC: Converts digital MAC signals to analog differential signals. Connected to MAC via MII/RMII/RGMII
3. Magnetics: Provides galvanic isolation (1.5kV typical) and common-mode rejection. Can be discrete transformer + common-mode choke, or integrated module
4. RJ45 connector: Often integrates the magnetics internally (“MagJack”)

PHY IC Layout

• Place the PHY IC between the MAC IC and the RJ45 connector, as close to the connector as possible
• Decoupling: place 100nF + 10µF at each power pin. PHY ICs typically have analog VDD, digital VDD, and I/O VDD — decouple each separately
• Crystal/oscillator: place the 25MHz crystal within 10mm of the PHY IC. Keep crystal traces short and away from high-speed signals
• RMII/RGMII bus routing: match trace lengths within 1mm for all bus signals. Use controlled impedance if trace length exceeds 25mm
• Configuration pins: route strap/configuration pins with pull-up/pull-down resistors near the PHY IC

Magnetics Selection and Placement

• Integrated MagJack: RJ45 connector with built-in magnetics. Simplest option — one component replaces three. Recommended for most designs
• Discrete magnetics + standard RJ45: Separate transformer module (Pulse H5007NL or equivalent) between PHY and connector. More layout flexibility, allows mounting connector away from PHY
• Placement: Magnetics must be close to the RJ45 connector — the traces between magnetics and connector are unshielded and vulnerable to EMI pickup. Keep under 25mm
• Isolation gap: Maintain a 6mm minimum clearance between the PHY-side traces and the connector-side traces on the PCB. This isolation gap provides the rated galvanic isolation voltage

Differential Pair Routing

• PHY to magnetics: Route TX+/TX- and RX+/RX- as 100Ω differential pairs. Match lengths within 0.15mm within each pair, and within 2mm between TX and RX pairs
• Trace width: For 100Ω differential on standard 4-layer FR-4 (0.2mm prepreg): approximately 0.12mm trace width, 0.2mm gap
• Maximum length: Keep PHY-to-magnetics traces under 50mm for 100BASE-TX, under 25mm for 1000BASE-T
• Series termination: Most PHY ICs include internal termination. If external termination is needed, place the resistors adjacent to the PHY output pins
• AC coupling capacitors: Some PHY ICs require AC coupling capacitors on the TX outputs. Place within 5mm of the PHY IC. Use matched capacitors (1% or better)

RJ45 Connector Layout

• Place the RJ45 at the board edge with mechanical support pins soldered to the PCB
• Route LED indicators (Link, Activity) from the PHY IC to the RJ45 LED pins. Most PHY ICs have configurable LED outputs
• The shield/housing of the RJ45 should connect to chassis ground through a low-impedance path. If there is no chassis, connect through a 1nF+1MΩ parallel network to signal ground
• For MagJack connectors, follow the manufacturer’s recommended footprint exactly — pin spacing and pad sizes are critical for the integrated magnetics

Galvanic Isolation

The magnetics provide galvanic isolation between the PHY/circuit side and the cable/connector side. This is critical for safety and noise rejection:

• Maintain a physical isolation gap (6mm minimum) on the PCB between the two sides. No traces, copper pour, or vias should cross this gap
• The isolation gap should be visible on the PCB — no solder mask covering it
• Ground planes on each side of the isolation gap must be separate and not connected
• Only the magnetics module bridges the isolation gap (through magnetic coupling)

Common Design Patterns

Frequently Asked Questions

Can I use a 2-layer board for Ethernet?

For 100BASE-TX (100 Mbps): possible with care. Route differential pairs on the top layer over a bottom ground pour. Use a MagJack to minimise trace count. For Gigabit Ethernet: use a 4-layer board for proper impedance control and signal integrity.

What is the difference between MII, RMII, and RGMII?

MII uses 16 signals at 25MHz (100 Mbps). RMII uses 9 signals at 50MHz (100 Mbps — preferred for fewer traces). RGMII uses 12 signals at 125MHz (1 Gbps). RGMII requires more careful length matching due to the higher clock frequency.

Do I need a separate crystal for the PHY?

Most PHY ICs require a 25MHz crystal or accept a 25MHz clock input. Some PHY ICs (like LAN8720A) can use a 50MHz RMII reference clock from the MCU instead of a dedicated crystal, saving a component.

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