Getting started with Lattice ICE40 FPGA and Verilog in India has never been more accessible, thanks to affordable Tang Nano boards and open-source toolchains. This tutorial walks through your first Verilog project on the ICE40, using only free tools that run on Linux, Windows, and macOS.
Table of Contents
- Why Lattice ICE40 for Indian Beginners
- Open Source Toolchain Setup
- Verilog Fundamentals
- First Project: LED Blinker
- Project 2: 4-bit Counter on 7-segment
- Project 3: UART Transmitter
- Frequently Asked Questions
Why Lattice ICE40 for Indian Beginners
The Lattice ICE40 family is the only FPGA with a fully open-source synthesis and place-and-route toolchain (Project IceStorm + Yosys + nextpnr). No expensive licences, no bloated IDEs requiring 50 GB downloads. The Tang Nano 4K (with Gowin FPGA but similar workflow) and TinyFPGA BX (iCE40LP8K) are popular ICE40-based boards available in India for ₹800–2,000.
Learning Lattice ICE40 FPGA Verilog with open-source tools prepares you for commercial FPGA work at Xilinx/AMD, Intel/Altera, and Microsemi without vendor lock-in.
Open Source Toolchain Setup
Install the complete open-source ICE40 toolchain on Ubuntu/Debian:
# Install tools
sudo apt install yosys nextpnr-ice40 icestorm
# Or install manually for latest versions:
# 1. Yosys (synthesis): https://github.com/YosysHQ/yosys
# 2. nextpnr (place and route): https://github.com/YosysHQ/nextpnr
# 3. Project IceStorm (bitstream tools): https://github.com/cliffordwolf/icestorm
# 4. iceprog (programmer): included in icestorm
On Windows, MSYS2 is recommended. Many Indian engineering colleges provide Linux lab access — the open-source toolchain is ideal for college lab use without commercial licence constraints.
Verilog Fundamentals
Verilog describes hardware, not software. Key concepts:
- Module: A hardware block with inputs and outputs (like an IC chip)
- always @(posedge clk): Execute on rising edge of clock (registers)
- assign: Combinational (immediate) logic
- reg vs wire: reg holds state (flip-flop), wire is a connection
// Verilog module structure
module my_module (
input wire clk, // Input clock
input wire rst, // Reset (active high)
input wire [7:0] a, // 8-bit input
output reg [7:0] y // 8-bit registered output
);
always @(posedge clk) begin
if (rst)
y <= 8'h00;
else
y <= a + 8'h01; // y = a + 1
end
endmodule
First Project: LED Blinker
// blink.v - LED blinker for ICE40 (12MHz clock)
module blink (
input clk, // 12 MHz oscillator
output led // LED pin
);
reg [23:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led = counter[23]; // Toggle at ~0.7 Hz (12M / 2^24 * 2)
endmodule
Build and flash commands for TinyFPGA BX (iCE40LP8K-CM81):
# Synthesise
yosys -p "synth_ice40 -top blink -json blink.json" blink.v
# Place and route
nextpnr-ice40 --lp8k --package cm81 --json blink.json --pcf blink.pcf --asc blink.asc
# Generate bitstream
icepack blink.asc blink.bin
# Program to board
tinyprog -p blink.bin
Project 2: 4-bit Counter on 7-segment Display
A binary counter driving a 7-segment display is the “Hello World” of FPGA displays. Create a decoder module that converts 4-bit binary (0–15) to 7-segment cathode patterns. This teaches combinational logic and multi-module designs.
// Seven-segment decoder (active low cathodes)
module seg7_decoder (
input [3:0] digit,
output reg [6:0] seg // seg[6:0] = gfedcba
);
always @(*) begin
case (digit)
4'h0: seg = 7'b1000000; // 0
4'h1: seg = 7'b1111001; // 1
4'h2: seg = 7'b0100100; // 2
// ... etc
default: seg = 7'b1111111;
endcase
end
endmodule
Project 3: UART Transmitter
Implementing UART in Verilog teaches state machines and clocked logic — fundamental FPGA design patterns. A UART transmitter at 115200 baud from a 12 MHz ICE40 requires careful clock division.
// UART TX state machine (simplified)
module uart_tx (
input clk,
input send, // Trigger transmit
input [7:0] data, // Byte to send
output reg tx = 1, // UART TX line (idle high)
output reg busy = 0
);
parameter CLK_DIV = 104; // 12MHz / 115200 ≈ 104
reg [7:0] shift_reg;
reg [3:0] bit_count;
reg [6:0] clk_count;
// State machine handles START, DATA[7:0], STOP bits
endmodule
Frequently Asked Questions
Where can I buy ICE40 FPGA boards in India?
Tang Nano 4K and Tang Nano 9K (Gowin GW1N, similar workflow) are available from Indian importers and sites like Amazon for ₹800–2,000. TinyFPGA BX is available via international shipping.
Is Verilog or VHDL better for beginners?
Verilog’s syntax is more concise and similar to C. Most open-source examples use Verilog. For Indian college students, check which your professor uses — both are equally valid, and most synthesiser tools support both.
Can I simulate Verilog without an FPGA board?
Yes. Use Icarus Verilog (free) for simulation and GTKWave for waveform display. Simulate before programming the board to verify logic correctness — essential discipline for FPGA development.
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